Quantum Hardware Modalities

Review status: rewritten from reviewer feedback · quality score: pending re-review

The mental model: a modality is a set of trade-offs, not a leaderboard

Every quantum hardware platform buys the same four resources — long-lived quantum states, controllable interactions, fast operations, and manufacturability — and every platform pays for them in a different currency. A candidate who can name the currencies can reason about any device, including ones that ship after this guide is written. A candidate who memorized "ions have better fidelity, superconductors are faster" will fail the first follow-up, because the right answer is always "it depends on the workload, and here is how I'd find out."

The four axes that actually decide things:

1. Coherence time vs. gate time. What matters is the ratio: how many sequential two-qubit operations fit inside one coherence window.
2. Single- vs. two-qubit gate fidelity. Two-qubit gates are typically 10x worse than one-qubit gates and dominate circuit error.
3. Native connectivity. All-to-all coupling vs. a fixed lattice changes how many physical gates a logical circuit needs.
4. Manufacturability and scaling path. A physics demonstration at 50 qubits and a factory producing calibrated 1000-qubit devices are different claims.

The rest of this guide works each axis, then shows the arithmetic that separates modalities in practice.

The landscape you're expected to name

Five platforms come up in interviews. One honest sentence on where each stands:

• Superconducting transmons. Josephson-junction circuits at ~10–20 mK, microwave-controlled. The most mature gate-model platform: IBM and Google have shipped devices with hundreds of qubits, with roadmaps to error-corrected architectures. Fast gates (tens to hundreds of nanoseconds), but each qubit is a custom fabricated object and calibration drifts.
• Trapped ions. Atomic qubits (often ¹⁷¹Yb⁺ or ⁴³Ca⁺) in Paul traps, laser- or microwave-driven, coupled through shared motional modes. Best two-qubit fidelities and effectively all-to-all connectivity, but gates are ~100–1000x slower and chains are hard to scale past tens of ions per trap; scaling proposals involve shuttling ions between zones.
• Neutral atoms. Optical tweezers trap arrays of hundreds of atoms (Rb, Cs, Sr), with Rydberg blockade providing entangling interactions. Strong for programmable analog Hamiltonian simulation today; the gate-model variant is real but younger. Atom loss mid-circuit is a distinctive failure mode.
• Photonics. Information lives in optical modes rather than two-level systems. Two directions: Gaussian boson sampling machines (Xanadu's Borealis and the X-series direction) targeting sampling tasks, and universal measurement-/fusion-based fault-tolerant schemes (PsiQuantum's stated direction). No cryogenic qubit refrigeration needed, but deterministic two-qubit gates are hard — most designs are probabilistic or measurement-based.
• Spin / semiconductor qubits. Electron or hole spins in quantum dots, or donor atoms in silicon. CMOS-compatible in principle and small in physical footprint, but currently at small demonstration scale; two-qubit fidelities trail ions and transmons.

Interviewers rarely want more depth than this on the physics. What they probe next is whether you can compare platforms, which is where the four axes come in.

Axis 1 and 2: the coherence budget and gate fidelity

The comparison that separates modalities is operations per coherence time set against wall-clock time — and the two point in opposite directions.

A superconducting transmon runs a two-qubit gate in roughly 25–500 ns against a coherence time near 100 µs. The ratio: 100 µs / 500 ns = 200 operations at the slow end, and 100 µs / 25 ns = 4000 at the fast end — so a few hundred to a few thousand sequential two-qubit operations fit inside one coherence window. A trapped ion runs the same gate in roughly 100–600 µs against coherence measured in seconds, giving a comparable or better operation budget — but a circuit of ten thousand two-qubit gates then takes a few milliseconds on the transmon and several seconds on the ion trap. For a variational loop needing a hundred thousand circuit executions, that difference is the whole experiment: the same algorithm is a two-hour job on one modality and a two-week job on the other, regardless of which device reports the better single-gate fidelity.

On fidelity: two-qubit gate error is the number to ask for, not single-qubit error. Typical current figures (order of magnitude, check the vendor's calibration data for the specific device): transmon two-qubit errors around 10⁻³–10⁻², ion traps around 10⁻³ or better, neutral-atom Rydberg gates in a similar range. Readout error is separate and often worse than gate error — 10⁻²–10⁻¹ on some transmon devices — and it multiplies into every shot. Crosstalk (unintended excitation of neighboring qubits during a gate) doesn't appear in per-gate numbers at all; you see it only when you run simultaneous operations.

Weak answer: "Ions have better coherence." Better coherence is only useful relative to gate duration — an ion trap's seconds-long T2 and a transmon's 100 µs T2 can support the same number of operations. The ratio is the metric.

Axis 3: connectivity is a software-visible constraint

Connectivity pushes in the reverse direction from speed. An ion chain with effectively all-to-all coupling executes an algorithm's non-local interactions directly. A fixed-lattice superconducting device — square grids (IBM's heavy-hex is a hexagonal variant) with degree 2–3 — routes non-local interactions through SWAPs at three CNOTs each. An algorithm dense in long-range interactions can lose more to routing than it gains from faster gates: a logical circuit of depth 100 on all-to-all hardware can become depth 400+ on a lattice, and every inserted SWAP consumes coherence budget and adds two-qubit error.

This is why "gate count" is not a hardware-independent metric. A circuit with 500 CNOTs compiles to different physical gate counts on every target:

• On an all-to-all ion trap, a CNOT between any pair is one native entangling gate plus local rotations.
• On a heavy-hex lattice, a CNOT between distant qubits costs 3 × (SWAP distance) extra CNOTs.
• On a device whose native gate is CZ or iSWAP rather than CNOT, each logical CNOT also decomposes into native gates plus single-qubit rotations.

The only honest comparison is: compile the actual workload to each target and compare the resulting two-qubit depth, estimated success probability, and shots required.

Axis 4: native gate sets and manufacturability

Each modality entangles qubits with a different physical mechanism, and the mechanism fixes the native two-qubit gate:

• Trapped ions: Mølmer–Sørensen (MS) gates — bichromatic laser drives excite the shared motional mode, producing an XX-type entangler. All-to-all because every ion shares the mode.
• Transmons: CZ (tunable couplers, e.g. Google), iSWAP, or cross-resonance (fixed-frequency qubits, IBM's workhorse — drive one qubit at the neighbor's frequency). Fixed-frequency transmons avoid flux noise but restrict which pairs you can calibrate well.
• Neutral atoms: Rydberg blockade gates — excite atoms to high-n states where dipole interactions shift the energy levels conditionally.
• Photonics: entangling is measurement-based or via nonlinear media; there is no persistent two-qubit gate in the same sense.

Decomposition cost is real: a logical Toffoli or arbitrary SU(4) on two qubits expands into several native entanglers plus single-qubit rotations, and single-qubit "virtual" Z rotations are often free (frame updates) while X/Y rotations are physical pulses. A compiler's quality is part of the measured performance — any benchmark that permits full-circuit optimization measures the compiler as much as the hardware.

On manufacturability: transmons leverage existing semiconductor fabrication but every device needs individual calibration (qubit frequencies scatter with fabrication variance), and wiring/cryogenic I/O is a serious scaling constraint — hundreds of coax lines into a dilution refrigerator don't become thousands for free. Ion traps have exquisite qubit uniformity (all ¹⁷¹Yb⁺ ions are identical) but the hard problem is trap scaling and ion shuttling. Neutral atoms are the natural-scaling winner — adding atoms is adding laser spots — but readout and mid-circuit atom loss are unsolved at scale. Spin qubits would ride CMOS lines, which is why companies chase them despite lower fidelities today.

Noise as the operating regime: reading real calibration data

Everything above is abstract until you look at what a cloud backend actually reports. On IBM Quantum or IonQ's backends you see, per qubit and per edge: T1, T2, readout assignment error, one- and two-qubit gate error (often from randomized benchmarking), and qubit frequency. What a candidate should be able to do with that data:

• Estimate circuit success. A circuit with 60 two-qubit gates on edges averaging 1% error gives roughly (0.99)⁶⁰ ≈ 55% before readout error — so you can predict, before running, that you need error mitigation or fewer gates.
• Spot the bad regions. Error maps are not uniform; a device's median 2Q error can hide edges at 5%. Layout choice matters as much as routing.
• Treat the data as a snapshot. A reported error map is taken at a calibration boundary. A circuit transpiled against yesterday's map may be routed onto a pair whose error has since doubled, and two jobs submitted either side of a recalibration ran on materially different machines. Record the calibration timestamp and backend version with every result; re-transpile rather than reusing a cached physical circuit after recalibration.

One caution on the source of those numbers: randomized benchmarking reports average error over random Clifford sequences, which is insensitive to coherent errors that accumulate rather than average out in a structured algorithm. Vendor summary metrics — quantum volume, algorithmic qubits, EPLG, CLOPS — each have their own protocol with its own compilation allowances, and a device can rank first on one and third on another without inconsistency. They are shortlist inputs, not decision inputs.

Annealers and analog simulators are a different computational model

A quantum annealer (D-Wave) evolves toward the ground state of an Ising or QUBO Hamiltonian. It does not run arbitrary circuits, has no gate set to compile to, and returns low-energy samples rather than a computed answer. Treating it as a slower gate-model QPU produces both wasted effort and unfair comparisons.

Its dominant hidden cost is minor embedding: a problem graph whose connectivity exceeds the hardware graph's must represent each logical variable as a chain of physical qubits coupled strongly enough to act as one. A densely connected problem with 100 logical variables can consume thousands of physical qubits, and chain strength becomes a tuning parameter whose wrong value produces broken chains and invalid samples. Any annealing result should report embedding overhead, chain break fraction, annealing schedule, and number of reads — alongside a classical baseline such as simulated annealing run for the same total time.

Neutral-atom arrays occupy a related position: they support programmable analog Hamiltonian evolution over hundreds of atoms as well as an evolving gate model, so a claim about one mode says little about the other. The general rule: the computational model, not the qubit technology, determines which problems a device can express, and a cross-model comparison is only meaningful when it fixes the problem, the accuracy target, and the total time budget.

What changes at scale, and when not to use quantum hardware at all

At current device sizes, the honest answer to "should I run this on a QPU?" is usually no. A problem with a good classical solver — MILP, SAT, TSP under a few hundred variables — is faster and cheaper classically. Quantum hardware earns its keep when the workload is a quantum algorithm with a proven or suspected speedup (chemistry simulation, sampling tasks), or when you're doing hardware research itself. Even then, at 100–1000 physical qubits with 10⁻³–10⁻² gate error, you're limited to circuits of depth a few hundred before noise wins, which is why error mitigation (zero-noise extrapolation, probabilistic error cancellation) and eventually error correction dominate the scaling conversation.

Error correction is the scale story: a logical qubit needs ~1000 physical qubits at current error rates (surface code, distance ~25 for useful logical error rates). "How many qubits does it have?" is therefore a nearly meaningless question — 1000 physical qubits is one logical qubit, and a vendor claiming "logical qubits" without error-correction evidence is relabeling their best physical qubit.

Interview follow-ups and how weak answers sound

Likely probes, and the failure modes to avoid:

• "Why not just use the platform with the best gate fidelity?" Weak answer: pick the ion trap. Strong answer: fidelity is per-gate; total success is per-circuit, and routing overhead, wall-clock time, and shots required can invert the ranking.
• "What's a quantum volume of 128 tell you?" Weak answer: it's good. Strong answer: it bounds the largest square random circuit (width ≈ depth) the device runs successfully with heavy-output probability above 2/3 — it says nothing about your workload's shape.
• "How would you pick a backend for a variational algorithm?" Weak answer: highest fidelity. Strong answer: compile the workload to each candidate target, estimate success probability and shots, multiply by queue and execution time, and include calibration stability and cost.
• "Is D-Wave a quantum computer?" Weak answer: yes/no. Strong answer: it's a quantum annealer — a restricted model for Ising/QUBO problems, not a universal gate-model machine; the comparison that matters is against classical heuristics at matched time budget.
• "Why do superconducting devices need calibration at all?" Weak answer: noise exists. Strong answer: fabrication variance scatters qubit frequencies and couplings, and parameters drift with thermal and control electronics changes — so the device you compiled against this morning is not exactly the device that runs tonight.

The production invariant underneath all of this: no modality or provider is preferred from headline qubit count or vendor-specific scores. Selection follows reproducible, workload-normalized executions — same problem, same accuracy target, same confidence, same end-to-end resource budget — with calibration timestamps, failed runs, and queue time retained as part of the evidence.