Technical interview guide

Quantum Gates & the Circuit Model

How quantum programs are expressed as circuits of unitary gates acting on qubits — the single- and multi-qubit gates every quantum algorithm is built from.

Read: 51 min
Practice MCQs: 25
Interview QA: 25
Edition: v2
Editorial status: Reviewed
Relevant for: Quantum Software Engineer

Scope: IBM Quantum and Qiskit current circuit/transpiler documentation; OpenQASM 3; QIR specification reviewed 2026-09-04.

Interview QA

Treat each question like a live interview question: answer out loud first (structure, assumptions, tradeoffs), then open the model answer to spot gaps and rehearse a tighter follow-up.

Curated: 2026-10-05 · Written: 2026-10-05 · Reviewed: 2026-10-04

QA-1

Why must all quantum logic gates in the standard circuit model be represented by unitary operators, and what physical principle does this enforce?

QA-2

How does gate application order in mathematical matrix composition correspond to temporal execution order in a quantum circuit diagram?

QA-3

What are the matrix representations, eigenbases, and physical actions of the Pauli X, Y, and Z gates on single-qubit states on the Bloch sphere?

QA-4

How does the Hadamard gate create equal superposition, and what is its geometric representation on the Bloch sphere?

QA-5

How do the Pauli-Z, S, and T gates relate algebraically, and why is the T gate specifically the bottleneck in fault-tolerant gate synthesis?

QA-6

Design and validate a circuit workflow for Hadamard.

QA-7

Design and validate a circuit workflow for phase gates.

QA-8

Design and validate a circuit workflow for rotation gates.

QA-9

Design and validate a circuit workflow for controlled operations.

QA-10

Design and validate a circuit workflow for SWAP.

QA-11

Design and validate a circuit workflow for gate order.

QA-12

Design and validate a circuit workflow for parallelism and depth.

QA-13

Design and validate a circuit workflow for measurement instruction.

QA-14

Design and validate a circuit workflow for reset.

QA-15

Design and validate a circuit workflow for global phase.

QA-16

Design and validate a circuit workflow for inverse circuits.

QA-17

Design and validate a circuit workflow for decomposition.

QA-18

Design and validate a circuit workflow for universal gate sets.

QA-19

Design and validate a circuit workflow for virtual and physical qubits.

QA-20

Design and validate a circuit workflow for basis translation.

QA-21

Design and validate a circuit workflow for routing.

QA-22

Design and validate a circuit workflow for optimization.

QA-23

Design and validate a circuit workflow for serialization.

QA-24

Design and validate a circuit workflow for semantic validation.

QA-25