Technical interview guide

Interrupts & Interrupt Service Routines

How hardware interrupts preempt normal execution, and the discipline required to write an ISR that doesn't corrupt shared state or blow the interrupt budget.

Read: 55 min
Practice MCQs: 25
Interview QA: 25
Edition: v3
Editorial status: Reviewed
Relevant for: Embedded Systems Engineer

Scope: CMSIS-Core 6.2 interrupt APIs; current FreeRTOS Cortex-M port guidance; current GCC interrupt attributes and Arm ABI reviewed 2026-09-04.

Interview QA

Treat each question like a live interview question: answer out loud first (structure, assumptions, tradeoffs), then open the model answer to spot gaps and rehearse a tighter follow-up.

Curated: 2026-10-05 · Written: 2026-10-05 · Reviewed: 2026-10-04

QA-1

Design and validate interrupt handling for interrupt path.

QA-2

Design and validate interrupt handling for vector table.

QA-3

Design and validate interrupt handling for handler ABI.

QA-4

Design and validate interrupt handling for source acknowledgement.

QA-5

Design and validate interrupt handling for pending and active state.

QA-6

Design and validate interrupt handling for priority encoding.

QA-7

Design and validate interrupt handling for preemption grouping.

QA-8

Design and validate interrupt handling for nesting.

QA-9

Design and validate interrupt handling for global masking.

QA-10

Design and validate interrupt handling for BASEPRI ceiling.

QA-11

Design and validate interrupt handling for RTOS syscall ceiling.

QA-12

Design and validate interrupt handling for ISR-safe APIs.

QA-13

Design and validate interrupt handling for deferred work.

QA-14

Design and validate interrupt handling for shared atomics.

QA-15

How do shared interrupts work, and how does an ISR determine whether its associated device asserted the interrupt?

QA-16

Design and validate interrupt handling for ring handoff.

QA-17

Design and validate interrupt handling for latency budget.

QA-18

Design and validate interrupt handling for WCET.

QA-19

Design and validate interrupt handling for interrupt storm.

QA-20

Design and validate interrupt handling for edge and level semantics.

QA-21

Design and validate interrupt handling for DMA completion.

QA-22

Design and validate interrupt handling for tick interrupt.

QA-23

Design and validate interrupt handling for fault handlers.

QA-24

Design and validate interrupt handling for test injection.

QA-25