Technical interview guide

Communication Protocols: SPI, I2C, UART

The three workhorse serial buses for talking to peripherals and other boards — how each is wired and clocked, and when to reach for which.

Read: 60 min
Practice MCQs: 25
Interview QA: 25
Edition: v3
Editorial status: Review pending
Relevant for: Embedded Systems Engineer

Scope: NXP UM10204 revision 7; CMSIS-Driver 6 SPI/I2C/USART interfaces; current Zephyr peripheral APIs reviewed 2026-09-04.

Interview QA

Treat each question like a live interview question: answer out loud first (structure, assumptions, tradeoffs), then open the model answer to spot gaps and rehearse a tighter follow-up.

Curated: 2026-10-05 · Written: 2026-10-05 · Reviewed: 2026-10-04

QA-1

How do UART, I2C, and SPI compare across wire count, throughput, clock synchronization, bus topology, and hardware complexity?

QA-2

How do you calculate the minimum and maximum pull-up resistor values for an I2C bus based on supply voltage, bus capacitance, and rise-time requirements?

QA-3

How do CPOL and CPHA define the four SPI clock modes, and what happens at the physical pin level during data sampling and shifting across them?

QA-4

Design and validate a serial-link strategy for SPI full duplex.

QA-5

Design and validate a serial-link strategy for SPI chip select.

QA-6

Compare dedicated Chip Select (CS) multi-slave SPI topology versus daisy-chain SPI topology in terms of hardware pins, software overhead, and throughput.

QA-7

Design and validate a serial-link strategy for SPI sharing.

QA-8

Design and validate a serial-link strategy for I2C electrical model.

QA-9

Design and validate a serial-link strategy for I2C transaction.

QA-10

Design and validate a serial-link strategy for I2C acknowledgement.

QA-11

Design and validate a serial-link strategy for I2C addressing.

QA-12

Design and validate a serial-link strategy for I2C clock stretching.

QA-13

Design and validate a serial-link strategy for I2C arbitration.

QA-14

Design and validate a serial-link strategy for I2C bus recovery.

QA-15

Design and validate a serial-link strategy for UART framing.

QA-16

Design and validate a serial-link strategy for UART packetization.

QA-17

Design and validate a serial-link strategy for UART errors.

QA-18

Design and validate a serial-link strategy for timeouts.

QA-19

Design and validate a serial-link strategy for interrupt completion.

QA-20

Design and validate a serial-link strategy for DMA ownership.

QA-21

Design and validate a serial-link strategy for DMA cache coherence.

QA-22

Design and validate a serial-link strategy for retry safety.

QA-23

Design and validate a serial-link strategy for integrity.

QA-24

Design and validate a serial-link strategy for logic-analyzer validation.

QA-25